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VLSI

VLSI

VLSI stands for Very Large Scale Integration, a process that combines millions of transistors onto a single chip to create an integrated circuit (IC). VLSI is a subfield of electrical engineering that involves designing, developing, and producing ICs

Private Course
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Responsible gavireddy hruthik
Last Update 15/04/2025
Completion Time 15 hours 19 minutes
Members 10
Advanced
  • Mastering Digital CMOS Layout Design
    13Lessons · 1 hr 50 mins
    • 1 PMOS
    • 2 NMOS
    • 3 Fabrication Process
    • 4 CMOS Inverter working
    • 5 CMOS Inverter Characteristics
    • 6 Power Delay Product
    • 7 Introduction to Microwind
    • Design Rule Check (DRC)
    • 9 CMOS Inverter Implementation
    • 10 Stick diagram
    • 11 Layout Design and Simulation Example 1
    • 12 Layout Design and Simulation Example 2
    • 13 Layout Design and Simulation Example 3
  • HDL
    9Lessons · 1 hr 31 mins
    • First Verilog Phrase
    • Verilog Rules and Syntax
    • Verilog Statements and Operators
    • Verilog Port modes and Data types
    • Verilog Structure
    • Verilog examples for combinatioanl circuits
    • Synchronous Circuits
    • Synchronous sequential circuits
    • Modular Design in Verilog
  • VSD - A complete guide to install open-source EDA tools
    25Lessons · 3 hrs 36 mins
    • Introduction to IC design components
    • Download oracle virtual box and ubuntu
    • Configure virtual box to add ubuntu ISO
    • Generic steps to start ubuntu installation
    • Setup ubuntu, launch terminal and install git
    • Clone vsdflow, learn chmod, and install vim
    • Understand basic UNIX commands and execute vsdflow
    • Observing cmake installation and lockunlock screen
    • Observing yosys, graywolf, qrouter, netgen magic, qflow installation
    • Observing openSTA and Opentimer installation with fast-forward edit
    • Test opensource EDA tool installation using vsdflow and spi_slave design
    • Debug qflow gui error, implement solution and test
    • Download oracle virtual box and CentOS7
    • Configure virtual box to mount and install CentOS
    • Setup CentOS, launch terminal, install git and clone vsdflow
    • Understand basic CentOS commands for installation and execute vsdflow
    • Observing yosys, graywolf, qrouter, netgen, magic, qflow installation
    • Strategy and steps to debug error, if any
    • Debug graywolf errors and test opensource tool installation using vsdflow
    • How to install virtual box
    • How to install ngSpice
    • How to install MAGIC layout editor
    • How to install Opentimer STA tool
    • How to install eSim schematic editor
    • How to install Yosys Synthesis Tool
  • SOC
    27Lessons · 3 hrs 42 mins
    • Introduction and Overview
    • Introduction to SOC and VLSI design flows
    • Verification - What, Why and How
    • Verification - Planning, Approaches, Metrics
    • Verification Methodologies - Simulation, Formal, Assertions
    • Directed vs Constrained Random Verification - Coverage
    • Other Trends - HW+SW Verification, Emulation
    • History and Language usage overview
    • Language Constructs - Data types and Operators
    • Language Constructs - Loops and Control Flows
    • Tasks and Functions
    • Arrays and Queues
    • Interfaces
    • Clocking Blocks
    • Program Blocks
    • Basic OOP Concepts
    • System Verilog Classes Explained
    • Virtual Interfaces
    • Random Constraints and usages - Part 1
    • Random Constraints - Part 2
    • Processes and Threads in System Verilog
    • System Verilog Mailboxes
    • Synchronization - Events and Semaphores
    • Exercise 1 Case Study on a Design to be verified
    • Standard Verification Methodologies - Need and evolution
    • Introduction to concept of OVM and UVM
    • Summary and learnings and future topics
  • SV VER
    7Lessons · 1 hr 11 mins
    • Introduction
    • Overview of Verification methodology, layered testbench
    • Factory - OOP design pattern in Verification
    • Callbacks - mechanism to customize VIPs, reusable code
    • Using macros to improve productivity
    • SequenceScenario modeling in Verification
    • Scheduler, Broadcaster, Summary, Conclusion
  • SVA+V
    4Lessons · 43 mins
    • Introduction and Overview
    • Introduction to Assertions
    • SVA Basics - Immediate and Concurrent Assertions
    • SVA Basics - Sequence and Property Blocks
  • TESTING
    7Lessons · 1 hr 30 mins
    • Introduction to Testing
    • Types of Testing
    • What is Fault Modeling
    • Introduction to Simulation and DSCH 35 Software
    • Implementation of Inverter Gate in DSCH 35 and its conversion to Microwind File
    • Implementation of AND Gate in DSCH 35 and Calculation of Stuck At Faults
    • Implementation of Half Adder and Full Adder in DSCH 35
  • TIME ANALYSIS
    6Lessons · 31 mins
    • Introduction
    • Definition of Timing Analysis
    • Why do we need Timing Analysis
    • Comparing Static Timing Analysis with Dynamic Timing Analysis (STA vs DTA)
    • Why is STA preferred over DTA
    • Course wrap-up and invitation to part-2
  • VLSI DESIGN
    5Lessons · 45 mins
    • Introduction
    • Digital Design Overview
    • Front-end design flow
    • Back-end design flow
    • Where is STA used in the digital design flow